Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
We are DDR/MCDDR Server Memory IO IP design team, within Intel’s Data center and AI group (DCAI), specializing in delivering innovative, custom bult, high performance, low power DDR/MCDDR PHY for Intel Xeon product line
Who You Are
We are looking for an Analog Design Engineer to contribute towards NextGen Data center Memory IO Design for Intel's High-Performance Data Center Microprocessors.
Responsibilities will include but not limited to:
Technology path finding, specification, and design of complex analog and mixed signal circuits, custom analog layout supervision, documentation, DFT/DFM and post silicon validation.
Analog circuit design responsibilities consist of high speed IO (HSIO) transmitters (Tx) and receivers (Rx), amplifiers (Op-Amps), equalizers (CTLE, DFE), filters, high performance low-jitter clocking, on-die voltage regulators (LDO) and references (BGR), signal integrity analysis, system level modeling, power delivery, supply noise sensitivity reduction (Bias generation and distribution), feedback loop analysis, stability, compensation, poles-zeros and other elements necessary to design, verify and productize high performance analog IO solutions.
Additional responsibilities include collaborating with other design disciplines, and contributing to design reviews. Be creative, accountable, and quick to make good decisions.
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's degree in Electrical Engineering or Computer Engineering with 3+ years of experience -OR- a Master's Degree in Electrical Engineering or Computer Engineering with 2+ years of experience -OR- a PhD degree in Electrical Engineering or Computer Engineering in lieu of work experience with:
Understanding of VLSI Analog circuit design tradeoffs, small signal analysis, digital design and building blocks (flops, latches, sizing, Boolean algebra)
Knowledge with design tools and flows such as Synopsys, Cadence
Preferred Qualifications
Knowledge of highspeed IO signaling, transmission line theory, power delivery power and signal integrity and power integrity concepts, PLL, Noise analysis, Jitter, clocking, ADC, DAC, Switched-Cap circuits
Memory IO training, Firmware, IO link training algorithms, Micro-architecture specification documentation
Reliability: RV, ESD, Aging, Electrical overstress
Cross discipline knowledge in any of these areas: Analog integration, RTL, System Verilog, Static timing analysis, APR, Floor planning, Metal routing, Power Grid Software: Matlab, Scripting
Post-Si knowledge: Si characterization, Lab equipment (Oscilloscopes, BERT, VNA, signal generators)
Experience in: Platform and Board design; Schematic capture, PCB layout, and typical lab tools.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits
Annual Salary Range for jobs which could be performed in the US:
$139,710.00-$197,230.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.