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Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
The IP and SoC Component Group within Intel's Data Center and AI organization (DCAI / IPSCG) is seeking an experienced IP Logic Design Engineer for its PCIe IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments. We are looking for an enthusiastic individual with a strong background in RTL design, broad experience in all aspects of IP development, and a proven capacity for understanding new technologies, to help deliver on our charter as Intel's center of innovation for next-generation IO.
Who You Are
As a member of our team, you will play a key role in developing PCIe gen7 IP from architectural specifications to a fully capable design that will meet area, power, performance, and timing requirements.
You will work with architects, designers, verification engineers, physical design engineers, firmware and test engineers to take the IP from concept all the way to silicon, crossing boundaries between disciplines and organizations to help ensure Intel's success in this critical domain.
You will be responsible for, but not limited to:
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Candidate must have a Bachelor's Degree in Electrical Engineering or Computer Engineering with 4+ years of industry experience -OR- Master's Degree in Electrical Engineering or Computer Engineering with 3+ years of industry experience -OR- PhD in Electrical Engineering and/or Computer Engineering.
Experience in Verilog, System Verilog
Experience in Logic Design, RTL Design
Knowledge of Design Tools and Design Analysis such as Design Compiler, CDC (Clock Domain Crossing), Closing Timing Violations
Preferred Qualifications
Scripting experience in languages like Python, Perl etc
Experience in Power Management IP, Power Management SoC, DFX knowledge
Experience in Verification Tools
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$161,230.00-$227,620.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.