Job Details:

Job Description:

The Memory IP Group (MIP) within the IP, Security, and Client Product Group (ISCP) is looking for a DFX Scan Design Engineer to work on DDR/LPDDR Hard IP’s. In this role you will work with an experienced Mixed Signal design team to develop scan/dfx solutions for DDR/LPDDR PHY designs going into CPU and Networking products. You will be responsible for taking the design from product definition through design, synthesis, hardening, post-silicon enabling and High Volume Manufacturing (HVM).

Responsibilities of the role include, but not limited to:

Help define DFx Scan design methodology and uarch to ensure good coverage [Scan and functional] for IP and meet products' DPM requirements
Setup and debug Spyglass-DFT or other ATPG tools, generate ATPG patterns via Mentor Graphic Tessent, RTL and GLS test validation to ensure quality design, debug and root cause stuckat and atspeed failure using Mentor GLS testbench in Synopsys VCS tools, and validate chain test in serial testbench
Define and Debug Scan Netlist insertion in Fusion Compiler.
Good and close loop communication across function group (Logic, Val, Ckt, SD, HVM) to ensure a right DFX arch introduce to the IP.
Perform yield analysis improvement and assisting the silicon debug
Analyze product requirement to balance DFX Scan requirements vs products' PPA and cost.

In addition to qualifications listed below the ideal candidate would have

Excellent analytical and problem-solving skills
Strong verbal and written communication skills
Effective team player with continuous learning mindset
Willingness to balance multiple tasks
Willingness to work in a fast-paced environment with cross functional teams.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

Bachelor's degree in electrical engineering, Computer Engineering, or any STEM related field, with 6+ years of relevant experience, OR
Master's degree in electrical engineering, computer engineering, or any STEM related field, with 4+ years of relevant experience.

For this position, relevant experience includes working on:

Scan and/or DFX Design or Validation
IP or SoC RTL logic development, verification, or integration using Verilog/System Verilog.
RTL coding including logic and behavioral modelling.
Problem solving/debugging various simulation failures.

Preferred Qualifications

Tools such as Tessent ATPG, Spyglass DFT, VCS and Fusion Compiler.
Knowledge of structural design concepts related to Timing, CDC/RDC(Clock/reset domain crossing), UPF (power domain modeling), LINT.
Experience with DFI/DDR/LPDDR Protocols.
Experience with DDR Phy or Memory Controller Logic Design
Experience leading RTL design execution
Structural design flows including Synthesis, Floor planning, and Speed path analysis.

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

Domestic relocation assistance is provided.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, California, Folsom, US, California, Santa Clara

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.