Mixed Signal Logic Design Engineer
Intel
US, Arizona, Phoenix
Posted on Intel website on 18 Apr 2025 (2 days ago)
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Who We Are
We are the HIGH-Speed IO IP department that deliver various High-Speed IO PHY across Intel.
Who You Are
Responsibilities include but are not limited to:
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Follows secure development practices to address the security threat model and security objects within the design.
Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IP SoC handoff.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor’s Degree in 6+ years of experience, Master’s Degree in 4+ years of experience and PHD 2+ years of experience degree
Preferred Qualifications
Experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation.
Experience in PCIE Design domain knowledge including PIPE, Controller, Low Power
Management is highly desired. PCIE Gen5 and Gen6 post silicon debug with controller is highly desired.
Experience in the following areas/ skills are desired:
USB Type C Design domain knowledge
Strong communicator
Git/Perforce/CVS know how
Perl/Python/TCL
Spyglass Lint, CDC, DFT, VCLP
Logic design using System Verilog
Low-power design using UPF and clock gating
Multiple clock domain design
State machine design
Simulation and debug experience using VCS/Verdi
Synthesis and speed path debug
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$186,070.00-$262,680.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.