Component Debug Engineer focused on post-Silicon product design enabling and optimization.
Evaluates and resolves component engineering design and physical design issues.
Ensures products have necessary design for debug features to enable deep silicon isolation capabilities.
Utilizes system setups, testing equipment, automated systems, and lab probe/FIB/prep tools to isolate microscopic silicon circuits while under test.
Performs fault isolation to root cause silicon failures, isolate defect modes, and engages with cross-functional teams such as test and validation engineers, circuit designers, wafer fabrication process engineers, and high-volume manufacturing for efficient and accelerated failure analysis.
Partners to resolve any quality issues, sharing ownership of failure analysis, temporary mitigation options, and permanent remedies.
Provides inputs on investigation areas for failure analysis or design process improvement and ensure performance to specifications. Develops new debug technologies, methodologies, and tools to advance the state of the art for silicon debug.
Bachelor's Degree in Electronics, Electrical, Microelectronics, Physics, Computer Engineering or a related technical degree.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Preferred Qualifications:
Experience in Silicon debug
DFT (Design for Test), especially experience in post-Si enabling
Digital/Analog Circuit design & validation
Mix signal design & validation
Functional and Reset content development
System validation & debug
Scan and Array Pre/Post Si validation, Si enabling and testing
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.