Job Details:

Job Description:

Join our dynamic Corporate Memory Organization as part of the Memory Compiler Team, where you will tackle significant engineering challenges in a fast-paced and technically demanding environment. Your role will involve mastering and optimizing SRAM/RF designs to meet specific process and product requirements, defining PV methodologies, and collaborating with Mask Design teams on layout. You will engage in circuit design tasks, including technical readiness, bit-cell simulation studies, critical path simulations, schematic entry, and design verification using both industry-standard and in-house PV tool suites. Additionally, you will contribute to methodology definition and ensure adherence to project schedules.Key Responsibilities:

Develop innovative design solutions to meet rigorous memory design specifications across various product segments, focusing on Memory Compiler Design, Flow, and Methodology development.
Lead the design, validation, and characterization of SRAM/RF Compilers.
Serve as a liaison with customers to ensure alignment and satisfaction.

Ideal Candidate Attributes:

Expertise in SRAM circuit design.
Proficiency in timing convergence and circuit quality metrics, including noise, power, and reliability.
Strong foundational knowledge of transistor-level behaviour and device characteristics.
Proficiency in scripting.
Exceptional logical thinking, analytical, and problem-solving skills.
Excellent verbal and written communication skills, along with strong interpersonal abilities.
Ability to multitask and prioritize effectively.

Qualifications:

Bachelor's degree (Master's degree preferred) in Electrical Engineering, Computer Engineering, or a related discipline with 10+ years of experience, OR a PhD in Electrical Engineering, Computer Engineering, or a related discipline.
Proficiency in scripting languages such as Perl, Tcl, or Python.
Comprehensive understanding of SRAM operations.
In-depth knowledge of transistor-level operations (VLSI coursework), design challenges under process variations, and low-power circuit techniques. These requirements can be met through a combination of relevant industry experience, internships, academic coursework, and research.
Experience with 5+ years of practical experience
Experience with designing SRAM circuits,
Experience in industry standard custom design tools and flows
Experience with circuit simulation and static timing analysis.
Strong knowledge of SRAM techniques with advanced custom circuit implementations
Strong knowledge of high-performance and low-power design features and techniques
Strong knowledge of semiconductor device fundamentals
Interacting with Physical Design team resolve memory PPA challenges

#DesignEnablement#DesignTechnologyPlatform

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.