Job Details:
Job Description:
Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process/packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Technology Platform (DTP) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs), foundational IPs (FIPs), and the Intel Foundry reference flows. These same deliverables carry out technology lead vehicle execution for Si validation. Enablement and optimization of reference flows and design flows on Intel technology play a crucial role in accomplishing DTP's charter.
Design flow development engineer will work in a team responsible for architecting, executing, and delivery of the EDA design flow for all DTCO activities, technology lead vehicle design, IP design, and product design in TD. The design flow will be built on top of a reference flow enabled on Intel technology and released from external EDA vendors. The design flow covers all aspects of front-end and back-end design from RTL to GDS, digital and analog, design creation, verification, and signoff. The candidate must be result-oriented and capable of disciplined flow execution to meet delivery milestones in a fast-paced environment on advanced technology nodes. Prior experience in EDA tool/flow and design environment development is highly desirable. Familiarity with automated SoC design methodology and/or analog/mixed-signal design methodology is a big plus.
Required Experience
- Extensive experience and a profound understanding of the complete physical design flow for SoC projects.
- Good knowledge in IP integration, floor-planning, I/O, bump, RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, etc.
- Experience in the development of EDA tools, flows and/or design env for digital or analog designs with demonstrated strong programing skills.
- Demonstrated ability to understand and interpret industry EDA trend in response to advanced node requirements, drive design flow initiatives to align.
Excellent written and verbal communication skills.
#DesignEnablement #DesignTechnologyPlatform
Qualifications:
- BS, MS, or PhD degree in electrical engineering, electronics engineering, computer engineering or similar field.
- Demonstrate a minimum of 15 years of industry experience in the development of ASIC full chip tapeout and/or physical design flow development experience, EDA tools, or design env for digital or analog designs
- Demonstrate strong programing skills.
#DesignEnablement #DesignTechnologyPlatform
Job Type:
Experienced Hire
Shift:
Shift 1 (Malaysia)
Primary Location:
Malaysia, Penang
Additional Locations:
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.