The DCAI-IPSCG (IP Group) is looking for energetic and passionate Micro architect /RTL Design leaders to develop high speed, state of the art complex digital IO controller ‘bug free’ designs (like PCIe, UPI, CXL controllers etc).
Your responsibilities will include but not limited to:
Review and participate in Specification reviews with architecture.
Define architecture to achieve best in class KPIs for IP.
Develop IP RTL.
Define IP Design constraints (SDC).
Perform the IP qualification using FE tools like Lint, CDC, Synthesis, STA, Power Analysis etc.
Drive IP verification teams & help define test plan scenarios/ constraints for randomization.
Definition of white box cover points/assertions for IP/Sub System.
Debug functional failures.
Support IP integration/debugs in end application (SoC) env.
Candidate should possess strong leadership, communication and interpersonal skills. Should have ability to work effectively with both internal and external teams/stakeholders.
Candidate should possess a Bachelor's degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 9+ years' experience or a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 7+ years' experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.