Job Details:

Job Description:

IPG/HSIO is chartered to provide high speed serial link IPs to various internal and external SoCs within the Intel eco-system. Key IPs that we work on include PCI Gen6 and 80 Gbps Type-C USB PHYs.Analog Design Engineer is responsible for analog circuit Design and corresponding Sign-off Verification (Functional, reliability, Mixed-Signal Verification etc) for custom circuits like CTLE, DCO, DFE, Tx and high speed clocking along with leading teams of junior engineers, driving the closure of macro-blocks and IPs and mentoring junior engineers. What we are looking for is strong hands-on technical skill in high speed mixed-signal circuit design, initiative, ability to think in terms of the overall system and take the decisions necessary to build a better solution for Intel, ability to work in teams, ability to handle pressure and communicate both up and down the chain effectively.

Objectives of the position

Own and deliver the Circuit Design/Sign-off verification of high-speed serial link building blocks.
Groom the junior team members towards technical excellence, drive innovation in the team and harvest publications/patents.
Work with internal stakeholders such as mask design for circuit implementation and logic design to design the analog/digital interface
Continuously drive the Turnaround time, robustness of circuit design and area/power of IPs.
Drive Post-silicon electrical validation, post silicon debug and high-volume manufacturing support for the IPs.Desired Competencies and Experiences:
Experience in working with cutting edge silicon technologies.
Deep understanding of Circuit design/ physical design of Analog Designs on advanced process technologies.
Expertise on high speed serial link design. Hands-on experience in blocks like Continuous Time Linear Equalizer (CTLE), Digitally Controlled Oscillator (DCO), Decision Feedback Equalizer (DFE), NRZ/PAM-3/4 Transmitter and high speed clocking.
Expertise on Reliability aware design and familiarity with Aging and RV tools. Ability to design floor plan and routing in Layout.
Good grasp on Industry standard tools such as Cadence design Environment (ADEXL or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools etc.
Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks
Strong communicator and proven leadership experience, self-driven, proactive nature to own and deliver high quality end to end Analog designs
Fast learner, good problem-solving skills, multitasking ability and attention to quality and detail.
Experience with MATLAB and system runs will be a major plus.

Qualifications:

Education:BS/MS - EE/CS and 10+ Years of industry experience.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

India, Hyderabad

Business group:

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.