Job Details:

Job Description:

Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to:

Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Follows secure development practices to address the security threat model and security objects within the design.
Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Qualifications:

The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent.
The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills.
The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills.
The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment.
Hands on experience in IP RTL, Microarchitecture, TFM, synthesis, cdc, lint, spyglass, rdc.

Skills:

Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc)
Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus.

Other technical requirements:

8-14 years of relevant pre-silicon logic design experience in ASIC domain.
Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification.
Experienced in EDA tools and flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc.
Experienced in developing micro-architecture based on High Level Architecture specifications.
Experienced in VLSI or Structural and Physical design flow and methodology.
Experienced in Power-aware design and reviewing validation flows.
Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.