Job Details:

Job Description: 

1. Constraints Generation and Validation: Collaborate with RTL/DFT designers to develop and validate timing constraints in RTL and netlist. Perform constraints health checks in "Timing Constraints Manager" to enhance the constraints quality and release turnaround time (TAT). Proactively clean up constraints based on inputs from the IP team.2. Clock Distribution Planning: Develop strategies for clock distribution that minimize divergence and latency. Address and resolve minimum pulse width (MPW) issues to ensure robust clocking.3. Pipeline Analysis and Optimization: Estimate and drive the synthesis and RTL design with a minimal number of pipelines, optimizing for power and area. Lead routing planning for pipelines in channel partitions, ensuring efficient pipeline convergence within defined bounds. Assess pipeline distances considering channel and partition congestion.4. Floorplan Analysis and Optimization: Analyze data flow and conduct floorplan analysis to guide the floorplan team in placing IPs strategically to improve system latency. Estimate and address channel congestion to enhance overall design efficiency.5. Skew and Clock Balancing/Planning: Analyze and develop predictive models for potential skew in post-clock tree synthesis (post-CTS). Plan segmented clock balancing in groups of IPs, incorporating additional pipelines if necessary to reduce latency and MPW issues.6. ECO Planning/creation and Convergence: Plan engineering change orders (ECOs) using suitable methods and industry-standard tools. Drive the synthesis and other static timing optimizations to achieve convergence.7. Signoff Methodologies and Timing Margins: Demonstrate a strong understanding of signoff methodologies/strategies. Support process-voltage-temperature (PVT) selection and timing margins, generate and code the timing signoff criteria required for the project.

Qualifications:

Minimum Qualifications: B.E/B.Tech or M.Tech/M.SPreferred qualifications:Requirements listed would be obtained through a combination of industry relevant job experience.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.