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Position Overview:
In this position, you will be a member of the silicon engineering division of the NEX Group. As part of this high-performance team, you will be involved in the digital design of leading-edge Cryptographic, Ethernet, and Packet Processing solutions on best-in-class Ethernet products. The team is looking to hire engineers with RTL development experience to augment and provide technical leadership within the existing team. Experience in adjacent engineering disciplines such as software development would also be considered.
Location:
Leixlip is the primary location for this position; however, we may consider suitable candidates that prefer a remote option in Ireland. In addition, we are happy to facilitate arrangements which support a Home Office setup from a work/life balance perspective.
Responsibilities:
Developing the micro-architectural specification of complex design block(s).
Logic implementation of complex design block(s) using RTL coding techniques.
Working with pre-Silicon validation engineers to develop cluster-level directed/random tests and environments.
Working with the Physical Design (Layout) team on Synthesis, Formal Verification, and Timing Convergence.
Interacting closely with other teams such as Architecture, DFx, Software, Firmware, and Post-Silicon Validation.
Educational Qualifications:
At minimum, an Honours degree (level 8 on www.nfq.ie) in Electronic Engineering, Computer Science, or equivalent.
Required Experience:
6+ years of RTL level Digital IC Design experience using System Verilog and/or Verilog.
Strong ASIC, SoC, or FPGA design experience.
Proven track record of successful first-time delivery of projects.
A self-starter with the ability to assume leadership roles.
Ability to work well in a diverse team environment.
Experience with industry-standard development tools and methodologies.
Preferred Experience:
Experience with languages such as C and/or C++, SystemC, OVM/UVM, SVAs, Perl, Shell scripting.
Experience in some of the following areas/tools: Synthesis, Formal Verification, DFT, VCS, PrimeTime, Design Compiler, Jasper (FPV).
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.